1. Field of the Invention
The present invention relates to a low noise semiconductor device, and more particularly to a high speed, low voltage semiconductor device, wherein power noise would pose a problem, in a semiconductor integrated circuit device for use in information processing apparatuses and the like.
2. Description of the Related Art
In recent years, power noise in semiconductor integrated circuit devices has come to pose an increasingly serious problem. This is attributable to (1) an increase in power noise quantity accompanying the rise in operating speed and the increase in power consumption, and (2) a decrease in power noise margin due to the use of lower voltage along with the evolution of the semiconductor process. Under these background circumstances, design techniques to keep power noise low enough and to secure stable operation of semiconductor circuits have become indispensable, and by one of such design techniques (Power Integrity design techniques; hereinafter referred to as PI design techniques or simply PI) the impedance of the power supply line is kept low over a broad bandwidth range. This method is made effective by the fact that the power noise voltage is determined by the product of the power supply current and the impedance of the power supply line.
Generally, electrically equivalent circuits to power feed routes are represented by serial and parallel circuits of resistance (R), inductance (L) and capacitance (C), and their impedance profile manifests a rugged pattern in which LC resonances and antiresonances on various power feed routes are in a row on the frequency axis.
In PI, it is desirable for the impedances of the power supply line to be uniformly low on the frequency axis as seen from within the chip (namely between A and A′ in FIG. 3) so that electric charges can be smoothly exchanged with outside in the chip, but it is difficult to keep them uniformly low on account of the presence of resonances and antiresonances in the impedance profile as stated above. What poses a problem here is that the impedance is at its maximum at an antiresonance frequency, and a problem of particular significance with the impedance of the power supply line in the chip is posed by an antiresonance impedance arising from the inductance of the power supply line from the chip to a on-board decoupling capacitor and an on-chip capacitance. This is a phenomenon occurring in the medium frequency band from tens of MHz to 100 MHz, one example of which is a curve convex upward, such as what is encircled by a dotted line in FIG. 2, indicated as having “No applicable technique”.
In a case of the related art, to suppress this antiresonance, the Q value is reduced by connecting a resistance to the power feed route to the decoupling capacitor in series (see JP-A-2006-032823(Patent Document 1)). By this technique, however, it is impossible to keep the impedance low for both low frequency and medium frequency because the impedance at low frequency is also raised by the insertion of the resistance in series. This impedance profile corresponds to “Uniform resistances in series inserted” in FIG. 2.
On the other hand, there are ways to realize low resistance at low frequency and high resistance at high frequency, namely a low Q state, while keeping impedance at low frequency low and suppressing antiresonance on the high frequency side by providing, around the power source-ground plane of the printed circuit board, a high resistance material or a high resistance structure (boring a hole or otherwise) or using a structure in which a high conductivity conductor with low conductivity conductors above and underneath as disclosed in JP-A-2001-244582 (Patent Document 2), JP-A-Hei-11-097810 (Patent Document 3) and U.S. Pat. No. 6,873,219 (Patent Document 4). Such techniques are effective in suppressing the antiresonance phenomenon that occurs on the power supply plane and work well against antiresonance phenomena of over 100 MHz.